Sierra Circuit Certification

Overcoming the challenges of high-speed designing

Electronic products are transforming into more complex devices due to the increase in component counts on PCBs. This is making room for high-density and high-frequency of circuit operation. Typically, signal frequencies from 50MHz to as high as 3GHz are considered to be high-speed signals. Soon, the demand for high performance from devices would require even higher speeds of operation and higher component counts.

These requirements demand challenging PCB design skills. This guide covers the performance requirements, such as signal integrity, and related issues of controlled impedance, power integrity, and EMI/EMC. To achieve these performance requirements, we cover how component placement, routing, stack-up design, and material selection is done for high-speed boards.

How to consider whether or not you’re designing for high speed

To execute a successful design for a circuit board, one has to first determine if it is in fact a high-speed design. If it is a high-speed design, then the PCB designer would need to take special care during the design process; and we would call them as high-speed design considerations – the main subject of this guide.

In most cases, based on their past experience, the design engineering team may determine the nature of the design.

In order to determine if the PCB requires high-speed design, we follow a two-step process:

First, the designer must state the values of one or more of the following parameters:

  • 1) The maximum frequency (Fm)content in the highest speed signals in the circuit.
  • 2) The fastest rise (or fall) time (Tr) of the digital signals in the circuit.
  • 3) The maximum Data Transfer Rate (DTR) applicable for signals in the circuit.

Second, you need to determine the wavelength (λm) on the PCB of the electrical (electromagnetic to be precise) signals for a given frequency, in our case Fm.


Factors that contributes to signal integrity degradation

Perhaps the most important cause of signal integrity issues in a PCB is faster signal rise times. When circuits and devices are operating at low-to-moderate frequencies with moderate rise and fall times, signal integrity problems due to PCB design are rarely an issue. However, when we are operating at high (RF & higher) frequencies, with much shorter signal rise times, it becomes a big issue.

For analytical purposes, we can divide various signal integrity issues into the following categories:

  • Impedance discontinuity
  • Reflection, ringing, over and undershoot
  • Crosstalk
  • Via stub
  • Skew and jitter
  • Signal attenuation
  • Power and ground distribution network
  • EMI noise

Errors to avoid when designing for controlled impedance

High-speed signals must be routed over a solid ground reference plane. Traces should not be routed over a split plane or a void in the reference plane. Routing high-speed signals across split planes can produce the following issues:

    • Interference with neighboring signals
    • Degradation of the electrical signal thus ruining signal integrity

The designer can use stitching capacitors across split planes if the signals have to be routed over them. The capacitors contribute a return path for the high-frequency current and minimize the current loop area along with any impedance discontinuity created by traversing the split plane. In the image shown below, the signals are routed around the void in the plane rather than across the split/void

High-speed PCB layout design guidelines

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    Component selection and placement

    It is good practice to minimize the use of sockets since they can introduce inductance. The designer should select the correct package, and accompanying component footprint while designing for high-speed. Components like op-amps are available in different packages. One type of an op-amp may support shorter trace lengths in a circuit than the other. Finally, the component footprint shapes should be optimized for thermal considerations. The best way to dissipate heat is to place power pads right under the IC footprints that are connected to an internal plane. Even the smallest change in the pad shapes can tighten up the routing and decrease the connection lengths. This will result in a compact design.

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    High-speed routing strategy and signal proximity

    A minimum distance should be maintained between traces to minimize crosstalk. The crosstalk level depends on the length and the distance between two traces. In some areas, the routing of traces reaches a bottleneck where the traces are closer than the allowed distance between them. In such situations, the distance between the signals outside the bottleneck should be increased. Even if the minimum requirement is met, the spacing can be increased a little further.

Take a peek at what’s inside the design guide

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